A sense amplifier circuit is used in a memory, for example a complementary metal oxide semiconductor (CMOS) memory, to detect or sense stored data from a bit cell. Performance of the sense amplifier circuit impacts memory access time and power dissipation. A single-ended sense amplifier circuit requires low power and one input data signal, and provides high noise immunity as compared to a differential sense amplifier circuit.
A conventional single-ended sense amplifier circuit 100, hereinafter referred to as the circuit 100, is illustrated in FIG. 1 (Prior Art). The circuit 100 is responsive to a control signal (SENB) to perform read operations. Initially, SENB is at logic level HI and DIN is at logic level LO. A transistor 105 is active. SENB then moves to a logic level LO. A transistor 110 becomes active and charges a bit line 115 through a diode 120. If operation is a read “0” operation then a bit cell coupled to the bit line 115 forces the bit line 115 to logic level LO. Hence, strength of the diode 120 is made less in order to prevent opposition of the bit cell by the diode 120 and to read “0” at output of an inverter 125. However, having the diode 120 with less strength leads to undesired delay during a read “1” operation. The bit line 115 is charged slowly due to presence of the diode 120. Also, strength of a transistor 130 is made high as compared to a transistor stack 135 to prevent opposition by the transistor stack 135 during a read “0” operation. However, having the transistor stack 135 with less strength leads to undesired delay during a read “1” operation. The undesired delay due to the diode 120 and the transistor stack 135 may lead to false reading. Moreover, the false reading increases with process, voltage and temperature variations.